View SAA7201H-T_6904816.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet objective speci?cation supersedes data of 1997 jan 29 file under integrated circuits, ic02 2001 mar 28 integrated circuits saa7201 integrated mpeg2 avg decoder
2001 mar 28 2 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 features general uses single external synchronous dram (sdram) organized as 1m 16 interfacing at 81 mhz; compatible with the sdram lite or pc fast external cpu interface; 16-bit data + 8-bit address dedicated input for audio and video data in pes or es format; data input rate: 9 mbytes/s in byte mode; 20 mbit/s in bit serial mode; audio and/or video data can also serve as input via cpu interface single 27 mhz external clock for time base reference and internal processing; all required decoding and presentation clocks are generated internally internal system time base at 90 khz can be synchronized via cpu port flexible memory allocation under control of the external cpu enables optimized partitioning of memory for different tasks boundary scan (jtag) plus external sdram self test implemented supply voltage 3.3 v package 160 qfp. cpu relation 16-bit data, 8-bit address, or 16-bit multiplexed bus; motorola and intel mode supported support for fast dma transfer to either internal registers or external sdram maximum sustained rate to the external sdram is 9 mbytes/s. mpeg2 system parsing of mpeg2 pes and mpeg1 packet streams double system time clock (stc) counters for discontinuity handling time stamps or cpu controlled audio/video synchronization support for seamless time base change (edition) processing of errors flagged by channel decoding or demux section support for retrieval of pes header and pes private data. mpeg2 audio decoding of 2 channel, layer i and ii mpeg audio; support for mono, stereo, intensity stereo and dual channel mode constant and variable bit rates up to 448 kbit/s audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 khz crc error detection selectable output channel in dual channel mode independent volume control for both channels and programmable inter-channel crosstalk control through a baseband audio processing unit storage ancillary data up to 54 bytes dynamic range control at output muting possibility via external controller; automatic muting in case of errors generation of beeps with programmable tone height, duration and amplitude serial two channel digital audio output with 16, 18, 20 or 22 bits per sample, compatible with either i 2 s or japanese formats serial spdif audio output clock output 256 or 384 f s for external d/a converter audio input buffer in external sdram with programmable size (default is 64 kbit) programmable processing delay compensation software controlled stop, pause, restricted skip, and restart functions. mpeg2 video decoding of mpeg2 video up to main level, main profile nominal video input buffer size equals 2.6 mbit for video main profile and main level (mp@ml) output picture format: ccir-601 4 : 2 : 2 interlaced pictures; picture format 720 576 at 50 hz or 720 480 at 60 hz 3 : 2 pull-down supported with 24 and 30 hz sequences support of constant and variable bit rates up to 15 mbit/s output interface at 8-bit wide, 27 mhz uyvy multiplexed bus horizontal and vertical pan and scan allows the extraction of a window from the coded picture
2001 mar 28 3 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 flexible horizontal continuous scaling from 0.5 up to 4 allows easy aspect ratio conversion including support for 2.21 : 1 aspect ratio movies vertical scaling with fixed factors 0.5, 1 or 2 to support picture scaling and up-sampling scaling of incoming pictures to 25% of their original size with anti-aliasing filtering to free screen space for graphics applications like electronic program guides non-full screen mpeg pictures will be displayed in a box of which position and background colour are adjustable by the external cpu video output may be slaved to internally (master) generated or externally (slave) supplied hv synchronization signals; the position of active video is programmable; mpeg timebase changes do not affected the display phase video output direct connectable to saa718x encoder family various trick modes under control of external cpu: C freeze i or p pictures; restart on i picture C freeze on b pictures; restart at any moment C scanning and decoding of i or i and p pictures C single step mode C repeat/skip field for time base correction. graphics graphics is region based and presented in boxes independent of video format screen arrangement of boxes is determined by display list mechanism which allows for multiple boxes, background loading, fast switching, scrolling and fading of regions support of 2, 4, 8 bits/pixel bit-maps in fixed bit-maps or coded in accordance to the dvb variable/run length standard for region bases graphics optimized memory control in mpeg video decoding allows for storage of graphical bit-maps up to 1.2 mbit in 50 hz and 2.0 mbit in 60 hz systems vl/rl encoding enables full screen graphics at 8 bit/pixel in 50 hz fast cpu access enables full bit-map updates within a display field period display colours are obtained via colour look-up tables; clut output is yuvt at 8-bit for each signal component thus enabling 16m different colours and 6-bit for t (transparency) which gives 64 mixing levels with video bit-map table mechanism to specify a sub-set of entries if the clut is larger than required by the coded bit pattern; supported bit-map tables are 16 to 256, 4 to 256 and 4 to 16 graphics boxes may not overlap vertically; if 256 entry clut has to be down loaded, a vertical separation of 1 field line is mandatory internal support for fast block moves in the external sdram during mpeg decoding graphics mechanism can be used for signal generation in the vertical blanking interval; useful for teletext, wide screen signalling, closed caption etc. support for a single down-loadable cursor of 1 kpixel with programmable shape; supported shapes are 8 128, 16 64, 32 32, 64 16 and 128 8 cursor colours are determined via a 4-entry clut with yuvt at 6, 4, 4 respectively 2 bits; mixing of cursor with video + graphics in 4 levels cursor can be moved freely across the screen without overlapping restrictions.
2001 mar 28 4 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 general description the saa7201 is an mpeg2 decoder which combines audio decoding and video decoding. additionally to these basic mpeg functions it also provides means for enhanced graphics and/or on-screen display. due to an optimized architecture for audio and video decoding, maximum capacity in the external memory and processing power from the external cpu is available for the support for graphics. quick reference data ordering information symbol parameter min. typ. max. unit v dd functional supply voltage 3.0 3.3 3.6 v v cc pad supply voltage 3.0 3.3 3.6 v i dd(tot) total supply current at v dd = 3.3 v - tbf - ma f clk clock frequency - 27.0 - mhz d f clk frequency deviation - 30 10 - 6 - +30 10 - 6 type number package name description version saa7201h qfp160 plastic quad ?at package; 160 leads (lead length 1.95 mm); body 28 28 3.4 mm; high stand-off height sot322-4
2001 mar 28 5 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 block diagram fig.1 block diagram. handbook, full pagewidth audio/video interface host interface system time base unit video input buffer and sync memory interface video decoder graphics unit audio input buffer and sync clock generation jtag mgd322 159 astrobe 77 75 74 78 84 83 81 80 sdras v ddco1 to v ddco4 sdwe cp81m reado readi sdaddr11 to sdaddr0 sddat15 to sddat0 sdcas sdudq cp81mext cputype dmareq dmaack dmardy dmadone vstrobe error mux hs vs 106 107 cs ds as r/w dtack cpaddr1 to cpaddr8 cpdat0 to cpdat15 irq0 to irq3 avdat0 to avdat7 2 1 8 clk 124 tclk 126 trst 127 tms 128 tdo 129 tdi 130 reset 138 9 10 4 4 3 6 5 display unit sd sclk ws spdif 143 142 145 146 audio decoder grph yuv0 to yuv7 119 fsclk 139 11 12 8 148 147 8 16 14 to 17 8 16 12 4 (9) (8) (7) (6) (5) (4) (3) (2) (1) saa7201 v ssco1 to v ssco4 4 16 v ssa 122 test0 to test8 104, 105, 118, 120, 132 to 136 19, 51, 101, 141 v dd1(pad) to v dd16(pad) v ss1(pad) to v ss16(pad) 16 v dda 121
2001 mar 28 6 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 pinning symbol pin description v i/o mux 1 multiplexed/non-multiplexed (active low) bus input 5.0 i cpu_type 2 intel/motorola (active low) selection input 5.0 i dma_ack 3 dma acknowledge input 3.3 i dma_req 4 dma request input and output 3.3 i/o dma_done 5 dma end input 3.3 i dma_rdy 6 dma ready output 3.3 o/z v ss1 7 ground for pad ring 3.3 - cs 8 chip select input 5.0 i ds 9 data strobe input 5.0 i as 10 address strobe input 5.0 i r/ w 11 read/write (active low) input 5.0 i dtack 12 data acknowledge output 5.0 o/z v dd1 13 supply for pad ring 3.3 - irq0 14 individually maskable interrupts 3.3 o/z irq1 15 individually maskable interrupts 3.3 o/z irq2 16 individually maskable interrupts 3.3 o/z irq3 17 individually maskable interrupts 3.3 o/z v ss2 18 ground for pad ring -- v ssco1 19 ground for core logic -- v ddco1 20 supply for core logic 3.3 - data0 21 cpu data interface 5.0 i/o data1 22 cpu data interface 5.0 i/o data2 23 cpu data interface 5.0 i/o data3 24 cpu data interface 5.0 i/o v dd2 25 supply for pad ring 3.3 - data4 26 cpu data interface 5.0 i/o data5 27 cpu data interface 5.0 i/o data6 28 cpu data interface 5.0 i/o data7 29 cpu data interface 5.0 i/o v ss3 30 ground for pad ring -- data8 31 cpu data interface 5.0 i/o data9 32 cpu data interface 5.0 i/o data10 33 cpu data interface 5.0 i/o data11 34 cpu data interface 5.0 i/o v dd3 35 supply for pad ring -- data12 36 cpu data interface 5.0 i/o data13 37 cpu data interface 5.0 i/o data14 38 cpu data interface 5.0 i/o data15 39 cpu data interface 5.0 i/o v ss4 40 ground for pad ring --
2001 mar 28 7 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 address1 41 cpu address interface 5.0 i address2 42 cpu address interface 5.0 i address3 43 cpu address interface 5.0 i address4 44 cpu address interface 5.0 i v dd4 45 supply for pad ring 3.3 - address5 46 cpu address interface 5.0 i address6 47 cpu address interface 5.0 i address7 48 cpu address interface 5.0 i address8 49 cpu address interface 5.0 i v ss5 50 ground for pad ring -- v ssco2 51 ground for core logic -- v ddco2 52 supply for core logic 3.3 - sdram_data0 53 memory data interface 3.3 i/o sdram_data15 54 memory data interface 3.3 i/o sdram_data1 55 memory data interface 3.3 i/o v dd5 56 supply for pad ring 3.3 - sdram_data14 57 memory data interface 3.3 i/o sdram_data2 58 memory data interface 3.3 i/o sdram_data13 59 memory data interface 3.3 i/o v ss6 60 ground for pad ring -- sdram_data3 61 memory data interface 3.3 i/o sdram_data12 62 memory data interface 3.3 i/o sdram_data4 63 memory data interface 3.3 i/o v dd6 64 supply for pad ring 3.3 - sdram_data11 65 memory data interface 3.3 i/o sdram_data5 66 memory data interface 3.3 i/o sdram_data10 67 memory data interface 3.3 i/o v ss7 68 ground for pad ring -- sdram_data6 69 memory data interface 3.3 i/o sdram_data9 70 memory data interface 3.3 i/o sdram_data7 71 memory data interface 3.3 i/o v dd7 72 supply for pad ring 3.3 - sdram_data8 73 memory data interface 3.3 i/o sdram_we 74 sdram write enable output 3.3 o sdram_cas 75 sdram column address strobe output 3.3 o v ss8 76 ground for pad ring -- sdram_ras 77 sdram row address strobe output 3.3 o sdram_udq 78 sdram write mask output 3.3 o v dd8 79 supply for pad ring 3.3 - read i 80 read command input 3.3 i symbol pin description v i/o
2001 mar 28 8 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 read o 81 read command output 3.3 o v ss9 82 ground for pad ring -- cp81mext 83 81 mhz clock return path input 3.3 i cp81m 84 81 mhz memory clock output 3.3 o v dd9 85 supply for pad ring 3.3 - sdram_addr8 86 memory address 3.3 o sdram_addr9 87 memory address 3.3 o sdram_addr11 88 memory address 3.3 o v ss10 89 ground for pad ring -- sdram_addr7 90 memory address 3.3 o sdram_addr10 91 memory address 3.3 o sdram_addr6 92 memory address 3.3 o v dd10 93 supply for pad ring 3.3 - sdram_addr0 94 memory address 3.3 o sdram_addr5 95 memory address 3.3 o sdram_addr1 96 memory address 3.3 o v ss11 97 ground for pad ring -- sdram_addr4 98 memory address 3.3 o sdram_addr2 99 memory address 3.3 o sdram_addr3 100 memory address 3.3 o v ssco3 101 ground for core logic -- v ddco3 102 supply for core logic 3.3 - v dd11 103 supply for pad ring 3.3 - test8 104 ic test interface 3.3 i/o test7 105 ic test interface 3.3 i/o hs 106 horizontal synchronization input and output 3.3 i/o vs 107 vertical synchronization input and output 3.3 i/o v ss12 108 ground for pad ring -- yuv0 109 yuv video output at 27 mhz 3.3 o/z yuv1 110 yuv video output at 27 mhz 3.3 o/z yuv2 111 yuv video output at 27 mhz 3.3 o/z yuv3 112 yuv video output at 27 mhz 3.3 o/z v dd12 113 supply for pad ring 3.3 - yuv4 114 yuv video output at 27 mhz 3.3 o/z yuv5 115 yuv video output at 27 mhz 3.3 o/z yuv6 116 yuv video output at 27 mhz 3.3 o/z yuv7 117 yuv video output at 27 mhz 3.3 o/z test6 118 ic test interface 3.3 i/o grph 119 indicator for graphics information output 3.3 o test5 120 ic test interface 3.3 i/o symbol pin description v i/o
2001 mar 28 9 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 v dda 121 supply for analogue blocks 3.3 - v ssa 122 ground for analogue blocks -- v ss13 123 ground for pad ring -- clk 124 27 mhz clock input 3.3 i v ss14 125 ground for pad ring -- tclk 126 boundary scan test clock input 3.3 i trst 127 boundary scan test reset input 3.3 i tms 128 boundary scan test mode select input 3.3 i td o 129 boundary scan test data output 3.3 o td i 130 boundary scan test data input 3.3 i v dd13 131 supply for pad ring 3.3 - test4 132 ic test interface 3.3 i/o test3 133 ic test interface 3.3 i/o test2 134 ic test interface 3.3 i/o test1 135 ic test interface 3.3 i/o test0 136 ic test interface 3.3 i/o v dd14 137 supply for pad ring 3.3 - reset 138 hard reset input (active low) 3.3 i fsclk 139 256 or 384 f s (audio sampling) output 3.3 o/z v ddco4 140 supply for core logic 3.3 - v ssco4 141 ground for core logic -- sclk 142 serial audio clock output 3.3 o/z sd 143 serial audio data output 3.3 o/z v ss15 144 ground for pad ring -- ws 145 word select output 3.3 o/z spdif 146 digital audio output 3.3 o/z error 147 ?ag for bitstream error input 5.0 i v_strobe 148 video strobe input 5.0 i v dd15 149 supply for pad ring 3.3 - av_data0 150 mpeg input port for pes data 5.0 i av_data1 151 mpeg input port for pes data 5.0 i av_data2 152 mpeg input port for pes data 5.0 i av_data3 153 mpeg input port for pes data 5.0 i v ss16 154 ground for pad ring -- av_data4 155 mpeg input port for pes data 5.0 i av_data5 156 mpeg input port for pes data 5.0 i av_data6 157 mpeg input port for pes data 5.0 i av_data7 158 mpeg input port for pes data 5.0 i a_strobe 159 audio strobe input 5.0 i v dd16 160 supply for pad ring 3.3 - symbol pin description v i/o
2001 mar 28 10 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.2 pin configuration. handbook, full pagewidth mgd321 saa7201 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mux cputype dmaack dmareq dmadone dmardy v ss1(pad) cs ds as r/w dtack v dd1(pad) irq0 irq1 irq2 irq3 v ss2(pad) v ssco1 v ddco1 cpdat0 cpdat1 cpdat2 cpdat3 v dd2(pad) cpdat4 cpdat5 cpdat6 cpdat7 v ss3(pad) cpdat8 cpdat9 cpdat10 cpdat11 v dd3(pad) cpdat12 cpdat13 cpdat14 cpdat15 v ss4(pad) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 test5 grph test6 yuv7 yuv6 yuv5 yuv4 v dd12(pad) yuv3 yuv2 yuv1 yuv0 v ss12(pad) vs hs test7 test8 v dd11(pad) v ddco3 v ssco3 sdaddr3 sdaddr2 sdaddr4 v ss11(pad) sdaddr1 sdaddr5 sdaddr0 v dd10(pad) sdaddr6 sdaddr10 sdaddr7 v ss10(pad) sdaddr11 sdaddr9 sdaddr8 v dd9(pad) cp81m cp81mext v ss9(pad) reado v dd16(pad) astrobe avdat7 avdat6 avdat5 avdat4 v ss16(pad) avdat3 avdat2 avdat1 avdat0 v dd15 (pad) vstrobe error spdif ws v ss15(pad) sd sclk v ssco4 v ddco4 fsclk reset v dd14(pad) test0 test1 test2 test3 test4 v dd13(pad) tdi tdo tms trst tclk v ss14(pad) clk v ss13(pad) v ssa v dda cpaddr1 cpaddr2 cpaddr3 cpaddr4 v dd4(pad) cpaddr5 cpaddr6 cpaddr7 cpaddr8 v ss5(pad) v ssco2 v ddco2 sddat0 sddat15 sddat1 v dd5(pad) sddat14 sddat2 sddat13 v ss6(pad) sddat3 sddat12 sddat4 v dd6(pad) sddat11 sddat5 sddat10 v ss7(pad) sddat6 sddat9 sddat7 v dd7(pad) sddat8 sdwe sdcas v ss8(pad) sdras sdudq v dd8(pad) readi
2001 mar 28 11 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 functional description general the saa7201 is an mpeg2 decoder which combines audio decoding, video decoding and enhanced region based graphics. the decoder operates with a single 16 mbit external synchronous dynamic random access memory (sdram) and runs from a single external 27 mhz clock. due to the optimized memory control for mpeg2 decoding, more than 1 mbit is available for graphics in 50 hz systems. mpeg2 data can be accepted up to 9 mbytes/s through a dedicated byte wide interface. the data on this interface can be either in pes (packetized elementary stream), mpeg1 packet or es (elementary stream) format as described in chapter references. two additional strobe signals distinguish between audio and video data. the internal video decoder is capable of decoding all mpeg compliant streams up to main level main profile as specified in chapter references. the audio decoder implements 2 channel audio decoding according to the standards in chapter references. all real time audio/video decoding and synchronization tasks are performed autonomously, so the external microcontroller only needs to perform high-level tasks like initialization, status monitoring and trick mode control. the main support task of the external microcontroller concerns the control of the graphical unit. this unit should be supplied with bit-maps, determining the contents of the graphical regions and by a simple set of instructions determining the appearance of the graphical data on the screen. most graphical information should be stored in the external memory which implies multiple data transfers between cpu and the external memory. by performing these data transfers on a direct memory access (dma) basis, full bit-maps can be transferred within one video frame period. the video output, containing a mix of mpeg video and graphical data, is at a yuv multiplexed format which can be directly connected to an external composite video encoder. the audio output, containing a mix of mpeg audio and programmable beeps, is in a serial, i 2 s or japanese format which can be directly supplied to most commercially available up-sampling audio da converters. a functional block diagram of the decoder is given in fig.1. its application environment is depicted in fig.24. in the following sections, a brief description of the individual internal blocks of the mpeg2 decoder will be given. audio/video interface in a basic set-top box application the saa7201 receives audio and video pes data in a byte wide format at rates up to 9 mbytes/s. a timing diagram is shown in fig.3. next to the 8-bit wide data bus an audio and video strobe is expected at the input. erroneous data may be flagged via the error indicator. handbook, full pagewidth vstrobe astrobe error avdat0 to avdat7 3 25 ns 3 25 ns 3 75 ns video byte (n) video byte (n + 1) audio byte (m) mgd323 fig.3 timing diagram of parallel input mode.
2001 mar 28 12 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.4 timing diagram of serial input mode. handbook, full pagewidth vstrobe astrobe avdat0 to avdat7 3 25 ns 3 25 ns 3 75 ns video bit (n + 6) video bit (n + 7) audio bit (m + 0) first bit of a byte error mgd324 alternatively data can be received in a 1-bit serial format at rates up to 20 mbit/s. in this mode, data is input at the lsb input of the av_data bus. audio and video data must be input in multiples of 8 bits. the first bit after switching from audio to video (or the other way around) must be the first bit of a byte since this transition will be used for the internal bit-to-byte conversion. audio/video data can also be received via the cpu interface in 8 or 16-bit mode. the peak rate is 27 mbytes/s in bursts of 128 bytes with a sustained rate up to 9 mbytes/s. however, the mpeg bit rate is still limited to 15 mbit/s for video and 448 kbit/s for audio. independent of the input mode all audio and video input data are stored sequentially in the audio or video input buffer area of the external memory. the audio and video data can be either in mpeg2 pes, mpeg1 packet or es format. memory interface unit the memory interface takes care of addressing and control of the 16-mbit external sdram. the sdram should be either jedec compliant either the lite/pc version. due to memory communication requirements this interface runs at 81 mhz. the sdram types used with the saa7201 should be organized as 1m 16, split internally in two banks, each having 2048 pages of 256 words of 16 bits. the target sdram type is nec m pd 4516161g5-a12-7fj (83 mhz jedec version) or nec m pd 4516421g5-a83-7fj-pc (83 mhz pc version). clock generation the clock generation unit generates all the internal processing clocks, the clock for the system time base counter and the audio oversampling clock for the audio dac. for this purpose a non-integer divider plus a pll is implemented. in order to get reliable audio and video decoding the 27 mhz input clock should be locked externally to the mpeg time base. host interface system the host interface system handles the communication between on one side the saa7201 plus sdram and on the other side the external cpu. the interface consists of a 16-bit wide data bus plus 8 address lines. it is compatible with both motorolas 68xxx and intels x86 family. an optimized interface with the saa7208 is also supported. via this interface a fast direct access to a large number of internal status and data registers can be achieved. moreover, the external sdram can be accessed via a specific register in combination with an internally implemented auto increment counter. the access to the external sdram is guaranteed up to a sustained data rate of 9 mbyte per second. however, in practice the achievable data rate can be much higher. next to the data and address lines, 4 interrupt lines are part of the host interface bus. each interrupt line can monitor up to 32 internal events which all can be masked individually. examples of internal events are audio/video bit stream information, decoder status, internal error conditions and input buffer occupation. the latter may be very useful in interactive applications to serve as input data request line.
2001 mar 28 13 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 system time base unit the system time base unit serves as a timing master for all internal processes. it consists of two 24-bit wide system time clock (stc) counters, running at 90 khz. the stcs will be used as internal synchronization reference for audio and video.the contents of the stc can be loaded by the external cpu which should insure that the phase of the saa7201 internal stc is identical to the main system time clock in the system demultiplexer. the cpu should correct for possible latency problems. because two counters are implemented, the previous time base reference which might still be required as reference for some time in case of time base discontinuity, can be maintained. thus all information for audio/video synchronization is available in the decoder chip and only minor support of the external controller is required. the synchronization of graphics for e.g. subtitling, should be controlled by the external cpu. video input buffer and synchronization control the size and position of the video input buffer in the external sdram is programmable. by default 2.6 mbit/s are reserved for the video input buffer but in principle any other value can be programmed. the current fullness of the video input buffer can be monitored by the cpu and an internal interrupt will be generated is case of either near over- or near underflow. data retrieval from the input buffer can be controlled by dts time stamps parsed from the pes or mpeg1 packet stream. for those frames where no dts time stamp is present in the video bitstream a dts is emulated by the saa7201. obviously this emulation mode can also be used when the input stream is a video elementary stream (es). the latter case should be handled by start and stop decode commands from the cpu. the external cpu can select to retrieve the video pes header and/or video pes private data for further software processing. audio input buffer and synchronization control the audio input buffer and synchronization control basically behaves identical to its video counter part. the default buffer size is 64 kbit in this case. synchronization will be controlled by pts time stamps in the audio packetized elementary stream. also in this case an pts emulation or a free running start/stop controlled mode are supported. audio decoder a functional block diagram for the audio decoding part is depicted in fig.5. fig.5 audio decoding unit. handbook, full pagewidth buffer and sync unit audio clock generator audio beep dram-bus 81 mhz mpeg audio decoder output interface sony or i 2 s-bus spdif mgd325 audio decoding unit +
2001 mar 28 14 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 audio decoding will be performed at a clock locked to the video decoding clock and only the output interface is running on the audio oversampling clock. the audio decoder unit performs the decoding of the selected mpeg audio stream in a range from 8 up to 448 kbit/s in a fixed or variable bit rate format. decoding is restricted to 2 channel, layer i, ii mpeg audio at sampling frequency of 48.0, 44.1, 32.0, 24.0, 22.05 or 16.0 khz. the audio decoder support the stop, mute, and skip function to support insertion apart from basic mpeg processing the audio decoder core contain also: support for: stop, mute and skip function. fully parameterized dynamic range compression unit to decrease the dynamic range of the output signal on audio frame basis. depending on the power level a programmable amplification and offset may be applied. fully programmable base band audio processing unit to control the gain in both output channels independently and/or to mix both channels. mpeg de-emphasis filtering on the output data, thus avoiding the need of external analog de-emphasis filter circuitry. storage buffer for the last 54 bytes of each audio frame. the cpu can retrieve eventual ancillary data from this buffer. the output of the audio decoder unit can be mixed with square waveform audio signals which are generated by a beep generator. programmable parameters for the beep generator are amplitude, frequency and duration. the audio output interface module produces stereo base band output samples on two different outputs at the same time: serial digital audio in i 2 s-bus or in japanese format in 16, 18, 20 or 22-bit spdif (sony/philips digital interface). any of the two outputs may be enabled or set to high impedance mode. the i 2 s-bus format with 18-bit sample precision is shown in fig.6. the difference between i 2 s-bus and the japanese format is that i 2 s-bus is msb aligned whereas the japanese format is lsb aligned. the 1-bit serial interface spdif contains 64-bit per audio sample period. complete frames must be transmitted at the audio sample rate. not only left/right information but also validity flags, channel status, user data and parity information is contained in an spdif frame (see chapter references). fig.6 i 2 s-bus format with 18-bit sample precision. handbook, full pagewidth b17 msb aligned mgd326 left sample n left sample n + 1 right sample n 0 31 32 63 sclk ws sd b0 b17 b0 b17 b0
2001 mar 28 15 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 video decoder the video decoding unit provides all actions required for compliant decoding of mpeg2 main level, main profile coded video bit streams. the decoding process consists of fixed and variable length decoding, run length decoding, inverse quantization, inverse discrete cosine transformation, motion compensation and interpolation. in general the arithmetic decoding result is stored as reference picture in the external memory. decoded b-frames are only stored for the conversion from the frame coded macro block (mb) to the scanning line format. in many cases a field storage is sufficient for this conversion but in some cases the user might decide to use a full frame storage to enable chroma frame up-conversion or full performance 3 : 2 pull-down in 60 hz systems. obviously when using less memory for the video decoding process more memory is available for non-video decoding tasks. the frame buffer management unit (fbm) manages the allocation of frame buffers in external sdram for both video decoding and display unit and can be programmed to use less memory in not fully mp@ml bitstreams: smaller pictures (e.g. 544 576), simple profile, etc. apart from decoding compliant mpeg video streams the decoder deals with some trick modes. supported are field or frame freeze at i or p pictures or freeze field on b-pictures. in the latter case decoding will continue as a background process and the output can be restarted at any moment. when receiving non-compliant mpeg streams the decoder can be switched to a scanning mode in which only i or i + p frames are decoded while skipping all other pictures. in the single step mode, the decoder decodes just one frame and awaits a next step command. the functional diagram of the video decoding unit is shown in fig.7. fig.7 video decoding unit. handbook, full pagewidth vld fld izz iq idct mc interp fbm to display unit to external memory from reference memory from input buffer mgd327
2001 mar 28 16 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 graphics unit the saa7201 incorporates the display support for pixel based graphics. possible applications are the user interface, logos and subtitling. graphical data should be grouped logically in regions and will be displayed in boxes at the screen. the definition of each region in the decoder consists of four parts being a region descriptor, a top-field descriptor, a bottom-field descriptor and a table-data descriptor: the region descriptor contains information relevant for the full region like format, size, position and pointers to the other descriptors. the top-field and bottom-field descriptor contain a pixel based bit-map for the contents of that region for both fields independently. the bit-maps can be stored in either straight forward or in a compressed bit-map format. the table-data descriptor defines the tables to be used for the transformation of bit-maps to display colours. all descriptors should be loaded under control of the external cpu in the external memory. the appearance of graphical data at the display is determined by the assembly of region descriptors in a so called display list. an example of such a display list for the 4 regions example is shown in fig.9. fig.8 graphics unit. handbook, full pagewidth region-1 (vbi-signals) region-2 active video region-3 (256 entry clut) region-4 mgd328 active video h-size (2) h-start (2) v-start (2) v-size (2) fig.9 display list. handbook, full pagewidth descriptor 1 map clut bottom-field top-field table data pixel data pixel data 128 bit gfx anchor address eodl position, size, format pointers to locations in sdram descriptor 2 descriptor 3 descriptor 4 mgd329
2001 mar 28 17 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 basically there is no restriction on the number of different regions but because regions may not vertically overlap the practical limit will be the number of lines within a field. however, one should realize that each region requires its own 128-bit region descriptor. the display list will be scanned twice per frame, once for each display field. the region descriptors should be ordered properly in the external sdram, starting from the graphics anchor address. the last descriptor in the list must have the end of display list indicator set. multiple pixel bit-maps, cluts and map tables may be stored in the external memory but per region only two bit-maps (one for each fields) and two tables (clut + map table) may be used. obviously bit-maps and tables may be shared by multiple regions. pixel data bit-maps can be described in 2, 4 or 8 bit/pixel in either a direct bit-map or coded in a one-dimensional (h) variable and run length encoded format according the pixel-data-sub-block syntax as specified in chapter references and illustrated in chapter appendix. the actual coding format is specified in the region descriptor for each region thus allowing different coding schemes within a picture. during display the 2, 4 and 8 bit/pixel bit-maps will be transformed, eventually with run length decoding, via a table look-up mechanism into a 4, 16 or 256 different yuv colours with 8-bit resolution for each component plus a factor t for mixing of graphics and mpeg video. in order to obtain maximum flexibility two cascaded tables are active in this bit-map to pixel conversion as indicated in fig.10. the tables are retrieved from the external memory just before the region is going to be displayed. one table per region can be updated and for small tables this occurs during the horizontal blanking interval. however, updating a 256 entry clut may take about one line period which means that a spatial separation of one line with the previous region is mandatory in this case. if the required tables for a certain region are already stored in the local memory, the table down load action can be skipped. additionally some special bits can be set in the region descriptor. transparency shift: this parameter overrules the pixel based transparency in order to support fading of the entire graphical region. zoom: this parameter initiates horizontal pixel repetition. it should be noted that a copy of pixels in vertical direction can be achieved by pointing to a single bit-map for both fields. regions can also be defined in the vertical blanking interval. in combination with 8 bit/pixel coding, arbitrary test signals on 13.5 mhz grid can be programmed. possible application areas are teletext, closed caption, wide screen signalling bits, video programming signals (vps) and vertical interval test signals (vits). as indicated above multiple regions can be specified in a display list which will be scanned sequentially every frame. in case of stationary graphics no updates of the display list are required, but the external cpu can update it dynamically to achieve scrolling and/or fading of one or more graphical boxes. the display list mechanism also allows for non real time transfer of large bit-maps by keeping that region out of the display list during loading. fig.10 bit-map to pixel conversion. handbook, full pagewidth 8 4 lsbs 2 lsbs 2 lsbs 4 lsbs 8 lsbs 8 clut 8 8 mgd330 map table 4 to 8 map table 2 to 8 8 y u v t 8 8 8
2001 mar 28 18 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 c ursor processing additionally to the above defined graphics boxes one cursor can be activated on the screen. since the cursor data is fully stored locally, no overlapping restriction apply to this box so the cursor can moved over the entire screen. the cursor can be as large as 1 kpixel with a 2 bits/pixel colour depth. obviously data transfer can be done on dma basis and need only be performed when a cursor is required or when its contents must be modified. the cursor xy dimensions (where the y dimension refers to frame lines) can be selected between 8 128, 16 64, 32 32, 64 16 and 128 8. on top of these shapes, a zoom with a factor 2 can be applied in both directions independently. the cursor pixels will be translated via a 4-entry clut to yuv colours and a transparency factor t. the resolution of the yuv parameters is 6, 4, 4 bits respectively. the t parameter is coded in 2 bits to enable the mixing with video and graphics in 4 steps being 100% (cursor only), 50%, 25% and 0% (fully transparent cursor). display unit before feeding the mpeg decoded and graphical data to the output, a display unit re-formats the mpeg specific 4:2:0 format to ccir-601 4 : 2 : 2 format and performs a mixing between video and graphics where required. the output picture can be up to 720 576 pixels at 50 hz or 720 480 pixels at 60 hz. a schematic representation of this unit is shown in fig.11. in a first step a selected window can be retrieved from the decoded mpeg data. this might be useful for e.g. pan and scan operations for aspect ratio conversion. in case the resulting number of pixels per line does not match the 720 pixels/line output format a horizontal scaler can be activated. this scaling unit can transform any number of bits below 720 to the required output format. internally a poly-phase filter is used which performs a 64 phases interpolation. not only up-conversion but also down-conversion is supported up to a scaling by a factor 2. thus horizontal scaling can be performed in a range from 0.5 up to 64. in practice the maximum up-conversion factor will be less or equal to 4. in vertical direction the picture can be expanded or scaled down, in both cases by a factor 2. expansion with a factor 2 might be relevant for the up-conversion of sif resolution pictures to full screen. the factor 2 scaling, if combined with the appropriate horizontal scaling, results is 1 4 picture thus freeing-up a large screen area for graphics. this might be very useful for electronic program guide applications. it should be noted that in case of picture compression an anti-aliasing filter can be activated. shifting: when the resulting mpeg picture is smaller than the 720 576 (480) display format, this picture can be located anywhere on the display screen. moreover, the non-covered area can be given any background colour. clipping: the amplitude of the mpeg decoded and re-scaled video signal is kept within the range 16 to 235 for luminance and 16 to 240 for both chrominance components. fig.11 display unit. handbook, full pagewidth window extraction scaling 64 step mixer 4 step mixer graphics cursor output format to digital cvbs encoder shifting clipping chroma up-conversion mpeg decoded picture mgd331
2001 mar 28 19 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 the chroma up-conversion unit converts the mpeg 4:2:0 format into the at the output required 4:2:2 format. this vertical up-conversion is performed by a simple 8-phase interpolation between two adjacent lines. the mixer units combine mpeg video with graphics and cursor information in two steps. in a first step the mpeg decoded information is mixed with graphical information. mixing can be done at pixel basis in 64 steps and is controlled by the internally implemented colour look up table. in a second step, the video plus graphics can be mixed in 4 steps with the internally generated cursor. the output formatting unit performs two main tasks, i.e. synchronization and formatting. synchronization is characterized by three signals being horizontal (h), vertical (v) and field parity (fp), all having programmable length and polarity. since the decoder can operate in master or slave mode, the synchronization signals can be generated by the decoder or should be delivered by an external device. in both cases the length and polarity should be programmed internally. the video output samples are supplied in a multiplexed yuv format to the output. next to this byte wide yuv stream, which can directly be supplied to most commercially available composite video encoder ics, three additional signals are delivered at the output. href indicates all active samples; cref can flag any combination of pixels: u, v, y odd and/or y even ; grph flags all the pixels inside a graphical box. additionally the full yuv bus can be set to a high impedance state under control of the signal yuv_ena. this might be useful for multiplexing the mpeg decoder output with any other signal source on static basis. fig.12 timing diagram of graphics information output. handbook, full pagewidth clk yuv href cref (example) grph '128' '16' u 0 y 0 v 0 y 2 mgd332
2001 mar 28 20 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 jtag the saa7201 supports the standard boundary scan test instructions: bypass, extest, sample, intest, runbist, idcode. memory requirements as indicated before the mpeg source decoder operates with 16 mbit of external memory. several processes require access to the external memory, mostly being the video decoding process. in normal main level, main profile video applications about 1.2 mbit of memory space is free for non-video processes. in practice most of this capacity will be used for graphics. in combination with the internal variable length decoding, full screen graphics at 8-bit per pixel is feasible. moreover, by having introduced a flexible memory allocation procedure the available memory capacity for graphics may be enlarged when decoding lower resolution mpeg pictures or when the input bit rate is less than 15 mbit/s. obviously for graphics-only applications all 16 mbit can be used for the storage of bit-maps and look-up tables. in table 1 an overview is given of the required memory capacity for some user defined modes. in 50 hz systems memory capacity can be saved by restricting the chroma vertical interpolation to field interpolation. this mode would only bring some extra chroma resolution in case the input stream contains progressive coded pictures. in 60 hz systems the reduction of storage capacity for b-frames to field capacity has not only consequences for the chroma vertical interpolation but also for the 3 : 2 pull-down operation mode. the operation repeat-first-field is not possible in all cases and a modified 3 : 2 pull-down is performed under the control of the saa7201. the user may decide to use this modified 3 : 2 pull-down mode in order to have more memory available for osd or graphics. table 1 required memory capacity for some user de?ned modes system 50 hz 60 hz bit rate (r) 15 mbit/s 15 mbit/s 9 mbit/s chroma interpolation frame ?eld ?eld frame ?eld ?eld 3 : 2 pull-down n.a. n.a. n.a. full mpeg modi?ed modi?ed picture format 720 576 720 576 544 576 720 480 720 480 720 480 audio input buffer 64 kbit 64 kbit 64 kbit 64 kbit 64 kbit 64 kbit video input buffer 1835 kbit 1835 kbit 1835 kbit 1835 kbit 1835 kbit 1835 kbit video implementation buffer (r/p) 600 kbit 600 kbit 400 kbit 500 kbit 500 kbit 300 kbit slave synchronization buffer (r/2p) 300 kbit 300 kbit 200 kbit 250 kbit 250 kbit 150 kbit reference and decoded picture 13456 kbit 12719 kbit 9609 kbit 12441 kbit 10634 kbit 8042 kbit total for video + audio 16255 kbit 15518 kbit 12108 kbit 15090 kbit 13292 kbit 10391 kbit remains for osdg (2 24 = 16777 kbit) 522 kbit 1259 kbit 4669 kbit 1687 kbit 3485 kbit 6386 kbit
2001 mar 28 21 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 limiting values in accordance with the absolute maximum rating system (iec 60134). thermal characteristics symbol parameter conditions min. max. unit v dd supply voltage (on all supply pins) 3.0 3.6 v v max maximum voltage on all pins 0 5.5 v p tot total power dissipation t amb =25 c - tbf w t stg storage temperature - 55 +150 c t amb operating ambient temperature 0 +70 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 30 k/w
2001 mar 28 22 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 characteristics symbol parameter min. typ. max. unit supply v dd supply voltage 3.0 3.3 3.6 v i dd supply current - tbf - ma inputs v ih high level input voltage 2.0 - v dd + 2.0 v v il low level input voltage - 0.5 - 0.8 v i li leakage current -- 20 ma c i input capacitance 0 - 10 pf outputs v oh high level output voltage 2.4 -- v v ol low level output voltage -- 0.4 v clk timing t c cycle time 37.036 37.037 37.038 ns d duty factor 40 - 60 % t r rise time 2 - 4ns t f fall time 2 - 4ns input timing with respect to clk rising edge t su set-up time 8 -- ns t h hold time 0 -- ns timing (see figs. 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 21 and 21 ) t su(a-cs) address/cs set-up time 20 -- ns t h(a-cs) address/cs hold time 75 -- ns t su(d-w) data write set-up time 20 -- ns t su(d-r) data read set-up time 20 -- ns t rel(d) data release time 0 - 10 ns t h(ct) control signal hold time 0 -- ns t w(ack) acknowledge pulse width 25 -- ns t rel(ack) acknowledge release time 0 - 10 ns t d(ack-r) delay time for acknowledge read 96 - 125 ns t d(ack-w) delay time for acknowledge write 48 - 75 ns t w(rw) write/read pulse width 25 -- ns output timing with respect to clk rising edge t h hold time 3 - t d ns t d delay time t h - 20 ns c l load capacitance 10 - 30 pf
2001 mar 28 23 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 handbook, full pagewidth address data mgd333 cpaddr1 to cpaddr8 cs r/w t su(a-cs) t h(a-cs) t su(d-ds) t h(d-ds) t rel(r/w) t rel(ack) t d(ack-w) t w(rw) dtack (intel rdy) ds (intel rdn) cpdat0 to cpdat15 fig.13 motorola write timing (non-multiplexed). handbook, full pagewidth address data mgd334 cpaddr1 to cpaddr8 cs ds dtack cpdat0 to cpdat15 r/w t su(a-cs) t h(a-cs) t a(d-r) t rel(ds) t rel(rw) t rel(ack) t d(ack-r) t w(rw) fig.14 motorola read timing (non-multiplexed).
2001 mar 28 24 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.15 intel write timing (non-multiplexed). handbook, full pagewidth address data mgd335 cpaddr1 to cpaddr8 cs t su(a-cs) t h(a-cs) t su(d-ds) t h(d-ds) t rel(rw) t rel(ack) t d(ack-w) t w(rw) dtack (intel rdy) r/w (intel nrn) cpdat0 to cpdat15 fig.16 intel read timing (non-multiplexed). handbook, full pagewidth address data mgd336 cpaddr1 to cpaddr8 cs dtack (intel rdy) r/w (intel nrn) t su(a-cs) t h(a-cs) t rel(ds) t a(d-r) t rel(rw) t rel(ack) t d(ack-r) t w(rw) cpdat0 to cpdat15
2001 mar 28 25 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.17 dma read access. handbook, full pagewidth data mgd337 cs dmaack dmardy cpdat0 to cpdat15 dmareq t su(a-cs) t h(a-cs) t su(d-ds) t h(d-ds) t rel(rw) t rel(ack) t d(ack-w) t w(rw) fig.18 dma write access. handbook, full pagewidth data mgd338 cs dmaack dmardy cpdat0 to cpdat15 dmareq t su(a-cs) t h(a-cs) t a(d-r) t rel(rw) t rel(ack) t rel(ds) t d(ack-r) t w(rw)
2001 mar 28 26 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.19 dma_done timing. handbook, full pagewidth mgd339 dmaack dmadone dmareq t su(a-cs) t h(a-cs) fig.20 saa7208 mode; read timing. handbook, full pagewidth mgd919 address address (8 to 0) data data (15 to 0) rdy ale t h(cs) t h(cs-ale) t w(ale) t w(sdr) t rel(d) t su(sdr-d) t su(ale-sdr) t su(a-cs) t h(a-cs) cs sysrd
2001 mar 28 27 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.21 saa7208 mode; write timing. handbook, full pagewidth mgd918 data (15 to 0) address (8 to 0) cs sysrd rdy data address ale t h(cs) t h(a-cs) t su(a-cs) t h(cs-ale) t w(sdr) t w(ale) t w(d-sdr) t h(d-sdr)
2001 mar 28 28 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.22 saa7208 mode; burst write timing. handbook, full pagewidth mgd920 data (15 to 0) address (8 to 0) cs sysrd rdy data data ale t w(ale) t su(d-sdr) t h(d-sdr) t su(d-sdr) t h(d-sdr) t w(sdr) t w(sdr) t rel(sdr) address address t h(cs) t h(cs-ale) t su(a-sdr) t h(a-sdr) t su(a-sdr) t h(a-sdr)
2001 mar 28 29 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 fig.23 intel read/write timing multiplexed. handbook, full pagewidth address address data data mgd341 ad (read) ad (write) cs ds (intel rd) dtack (intel rdy) as (intel ale) t d(ack-r/w) t rel(ds) t rel(ack) t w(as) t su(d-r) t a(d-r) t h(a-cs) t h(d-ds) t su(a-cs) t su(d-ds) t rel(rw) t w(rw) wr references 1. mpeg iso/iec 11172-1 international standard; mpeg-1 systems. 2. mpeg iso/iec 13818-1 international standard; mpeg-2 systems. 3. mpeg iso/iec 11172-2 international standard; mpeg-1 video. 4. mpeg iso/iec 13818-2 international standard; mpeg-2 video. 5. mpeg iso/iec 11172-3 international standard; mpeg-1 audio. 6. mpeg iso/iec 13818-3 international standard; mpeg-2 audio. 7. dvb subtitling system; working draft 2.0; tm 1398 rev 2 .
2001 mar 28 30 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 application information fig.24 application diagram. handbook, full pagewidth saa7208 (demux/mips) 4 mbits eprom 4 mbits dram saa7201 saa7183 (euro-denc) 16 mbits sdram audio d/a 8 + 3 4 2 12 address data control 8 16 16 irq h,v valid yuv cvbs mgd342 rgb y/c strobe 27 mhz 27 mhz i 2 c-bus i 2 c-bus h, v, fp ttx/ttxrq high speed data
2001 mar 28 31 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 appendix syntax of pixel-data-sub-block data type pixel-code-string of n-coded words end of string 2 bit/pixel 01 1 pixel in colour 1 10 1 pixel in colour 2 0001 0000 11 1 pixel in colour 3 00 00 00 00 01 1 pixel in colour 0 00 00 01 2 pixels in colour 0 00 1l ll cc l pixels (3 to 10) in colour c 00 00 10 ll ll cc l pixels (12 to 27) in colour c 00 00 11 ll ll ll ll cc l pixels (29 to 284) in colour c 4 bit/pixel 0001 1 pixel in colour 1 0001 0001 1111 1 pixel in colour 15 0000 0000 0000 1100 1 pixel in colour 0 0000 1101 2 pixels in colour 0 0000 0lll (l>0) l pixels (3 to 9) in colour 0 0000 10ll cccc l pixels (4 to 7) in colour c 0000 1110 llll cccc l pixels (9 to 24) in colour c 0000 1111 llll ll11 cccc l pixels (25 to 280) in colour c 8 bit/pixel 00000001 1 pixel in colour 1 00000000-- --00000000 0001 0010 11111111 1 pixel in colour 255 00000000 0lllllll l pixels (1 to 127) in colour 0 00000000 1lllllll cccccccc l pixels (3 to 127) in colour c
2001 mar 28 32 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 package outline unit a 1 a 2 a 3 b p ce (1) (1) (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.40 0.25 3.70 3.15 0.25 0.40 0.25 0.23 0.13 28.1 27.9 0.65 0.3 1.95 32.2 31.6 1.5 1.1 8 0 o o 0.15 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.1 0.7 sot322-1 mo-112 97-08-04 99-12-27 d (1) 28.1 27.9 h d 32.2 31.6 e z 1.5 1.1 d pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 40 c d h b p e h a 2 v m b d z d a z e e v m a x 1 160 121 120 81 80 41 y w m w m 0 5 10 mm scale sot322-1 160 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height qfp160: plastic quad flat package; a max. 3.95
2001 mar 28 33 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 mar 28 34 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2001 mar 28 35 philips semiconductors objective speci?cation integrated mpeg2 avg decoder saa7201 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ics with mpeg-2 functionality ? use of this product in any manner that complies with the mpeg-2 standard is expressly prohibited without a license under applicable patents in the mpeg-2 patent portfolio, which license is available from mpeg la, l.l.c., 250 steele street, suite 300, denver, colorado 80206.
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2001 72 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 7 - 9 rue du mont valrien, bp317, 92156 suresnes cedex, tel. +33 1 4728 6600, fax. +33 1 4728 6638 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: philips hungary ltd., h-1119 budapest, fehervari ut 84/a, tel: +36 1 382 1700, fax: +36 1 382 1800 india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753504/03/pp 36 date of release: 2001 mar 28 document order number: 9397 750 08176

▲Up To Search▲

Price & Availability of SAA7201H-T

	To Download SAA7201H-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .